Typical switching regulators include buck converter, booster converter and inverter converter. FIG. 1 shows a conventional buck converter, which includes two transistor switches Q1 and Q2 controlled by a pulse width modulation control circuit (PWM) 10. The switching of the transistors Q1 and Q2 controls the current amount and direction on the inductor L, so that power is transmitted to the output terminal OUT. The PWM 10 receives a voltage signal which is fed back from the output terminal, and compares it with a reference voltage Vref, to determine the duties of the transistors Q1 and Q2.
In early days, the transistors Q1 and Q2 are completely complementary to each other, and such switching regulator is called “synchronous switching regulator”. Referring to FIG. 2, when the transistor Q1 is ON, the transistor Q2 is OFF, and vise-versa. (In the context of this specification, “ON” is fully conductive, and “OFF” is non-conductive, regardless of leakage current.) In such synchronous switching regulator, the current IL of the inductor has a waveform as shown by the third waveform of FIG. 2: When the transistor Q1 is ON and the transistor Q2 is OFF, the current flows towards the output terminal OUT (shown by “+” in the figure), and the current amount increases. When the transistor Q2 is ON and the transistor Q1 is OFF, the voltage at the node Lx at the left side of the inductor drops to 0, and the voltage at the output terminal OUT is higher than the voltage at the node Lx, so the current trend reverses, first the current amount towards the output terminal decreases, and later the current starts to flow towards the other direction (shown by “−” in the figure).
FIGS. 3 and 4 respectively show a booster type switching regulator 2 and an inverter type switching regulator 3, which operate in a similar manner as above, in which a PWM 10 controls two transistors Q1 and Q2 to transmit power to the output terminal OUT according to comparison between a feedback voltage and a reference voltage Vref. These regulators are well known by one skilled in this art, so the details of their operation are omitted here.
Referring to FIGS. 1 and 2, there is a drawback to synchronously switch the transistors Q1 and Q2, because when the direction of the inductor current is negative, i.e., when current flows from the output terminal OUT to ground via the inductor L and the transistor Q2, it means that there is loss of power from the output terminal OUT.
Accordingly, U.S. Pat. No. 6,580,258 proposes a countermeasure as shown in FIG. 5, in which the transistors Q1 and Q2 are properly controlled so that the Q2 is turned OFF when the direction of the inductor current is about to change from positive to negative. Thus, there is no power loss from the output terminal OUT. As shown in the figure, there is a time period T wherein the transistors Q1 and Q2 are both OFF, which is called the “sleep mode”.
However, this prior art has its drawback. When the transistors Q1 and Q2 are both OFF, entering the sleep mode, the actual waveforms of the current flowing on the inductor L and the voltage at the node Lx are not ideal. As shown in FIG. 7, when the transistors Q1 and Q2 are both OFF, the current IL of the inductor L presents a ringing waveform, and the voltage VLx at the node Lx presents a waveform of damped simple harmonic motion. To explain it, as shown in FIG. 6, in practical case there is a parasitic resistor Rpa connected in series with the inductor L, and a parasitic capacitor Cpa connected in parallel with the transistor Q2. Let the inductance of the inductor L, the resistance of the parasitic resistor Rpa, and the capacitance of the parasitic capacitor Cpa be L, Rpa, and Cpa, respectively; then, the voltage VLx at the node Lx should be:VLx=(VOUT/LCpa)×{1/[S2+S(Rpa/L)+1/LCpa]}wherein VLx is the voltage at the node Lx, Vout is the voltage at the output terminal OUT, and S is a time-to-frequency conversion variable.
The voltage VLx at the node Lx expressed by the above equation presents a high frequency damping waveform, having an angular frequency ω0 and a damping quality Q respectively as:ω0=1/(LCpa)1/2 Q=L1/2/[Rpa(Cpa1/2)]
Because the voltage VLx at the node Lx presents a high frequency damping waveform, it generates EMI noises which are undesired.
In view of the foregoing drawback, the present invention proposes a switching regulator with reduced EMI, and a control circuit and a control method for the switching regulator.